Can Leading-Edge Chip Processes Be Compared by Nanometer Labels Alone?
Compare leading-edge processes using power, performance, area, and cost per good die rather than node names alone. Learn how design conditions and production maturity affect the economics.
Leading-edge processes should be compared by performance, power, area, and actual cost per good die for the same task, rather than by a small node label alone. Comparisons can be distorted by treating different companies' node names as identical physical dimensions or extrapolating test-chip performance to volume-production results for every product.
Align the Conditions for Comparing Performance and Power
When a process announcement reports performance gains, check whether they were measured at the same power; when it reports power reductions, check whether they were measured at the same performance. Combining improvements measured under different conditions as though they can be achieved simultaneously overstates the benefit. TSMC's annual report discusses process development and production technologies, so start by reading the intended uses and development stage of each technology. Actual customer products are influenced by circuit configuration, the share of memory and I/O, and the maturity of design tools, making it difficult to explain finished-product performance through the process alone.
Connect Area Reductions to Cost per Good Die
A smaller die may increase the number of potential dies obtainable from one wafer. However, if wafer processing and design costs also rise, the final chip cost does not necessarily fall. ASML's explanation of lithography principles helps explain how circuit patterns are formed on wafers. In investment analysis, ask how much the increase in good dies offsets the cost of a more complex process. You can distinguish a scenario with high initial costs caused by low yields from one in which the economics change as production experience accumulates.
Not Every Circuit Needs the Latest Process
Identify which parts of a product benefit most from scaling. Compute circuits and I/O circuits may have different optimal trade-offs between cost and performance. An increase in a company's share of leading-edge production does not by itself establish that its overall product profitability has improved. Sales volume also matters for recovering the design costs associated with a process choice. A product with low expected sales has fewer units over which to spread higher upfront design costs, so the most technically advanced choice may not always be the most economical. Access to design tools and proven circuit IP is another indicator of production readiness. Additional work may be required between a process announcement and the point when customers can actually design and sell products using it.
Worked example
Hypothetical example: An existing process costs KRW 10 million per wafer and yields 500 good dies, or KRW 20,000 per good die. If a new process costs KRW 15 million per wafer and yields 600 good dies, the cost per good die is KRW 25,000. The number of good dies increases 20%, but unit cost is 25% higher. The new process must yield 750 good dies to match the existing process on processing cost. Note the limitation that this comparison excludes design and packaging costs.
What to check
- Check whether comparisons use the same performance or the same power
- Distinguish volume-production schedules from development demonstrations
- Calculate actual cost per good die rather than relying on die area
- Assess the sales volume needed to recover additional design costs
Sources and primary materials
This is educational material about research methods. For an actual company decision, verify the filings and primary sources for the relevant period.